High level modeling of elastic circuits in SystemC

Synchronous design is currently by far the mainstream design paradigm of digital circuits. However, the move to modern nano-meter technologies has brought unprecedented delay variability issues. That makes maintaining clock synchronization challenging and costly in terms of power and area. Elastic circuits is an emerging method for tackling delay variability while avoiding the technology disruption and design issues of asynchronous circuit design. We discuss a model-based approach to elastic circuits that starts from a system (circuit) specified in the synchronous language Quartz. The system is then elasticized i.e. partitioned to an elastic network consisting of inter-connected synchronous modules. The scope of this work is on synthesizing the elastic network by generating code for SysteMoC which is an actor-oriented modeling library based on SystemC. That enables rapid simulation of different partitioning and scheduling strategies at a high-level of abstraction. We have developed a synthesis library capable of generating code for most Quartz features. We show some experimental results based on synthesizing different synchronous models that have been elasticized using a basic partitioning strategy.